library verilog;
use verilog.vl_types.all;
entity i2c_tb is
    generic(
        SLAVE_IDLE      : vl_logic_vector(0 to 2) := (Hi0, Hi0, Hi0);
        SLAVE_ADDR      : vl_logic_vector(0 to 2) := (Hi0, Hi0, Hi1);
        SLAVE_DATA_RD   : vl_logic_vector(0 to 2) := (Hi0, Hi1, Hi0);
        SLAVE_DATA_WR   : vl_logic_vector(0 to 2) := (Hi0, Hi1, Hi1);
        SLAVE_ACK       : vl_logic_vector(0 to 2) := (Hi1, Hi0, Hi0);
        SLAVE_NACK      : vl_logic_vector(0 to 2) := (Hi1, Hi0, Hi1);
        SLAVE_STRETCH   : vl_logic_vector(0 to 2) := (Hi1, Hi1, Hi0);
        TEST_DATA_WRITE : vl_logic_vector(0 to 7) := (Hi1, Hi0, Hi1, Hi0, Hi0, Hi1, Hi0, Hi1);
        TEST_DATA_READ  : vl_logic_vector(0 to 7) := (Hi0, Hi1, Hi0, Hi1, Hi1, Hi0, Hi1, Hi0)
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of SLAVE_IDLE : constant is 1;
    attribute mti_svvh_generic_type of SLAVE_ADDR : constant is 1;
    attribute mti_svvh_generic_type of SLAVE_DATA_RD : constant is 1;
    attribute mti_svvh_generic_type of SLAVE_DATA_WR : constant is 1;
    attribute mti_svvh_generic_type of SLAVE_ACK : constant is 1;
    attribute mti_svvh_generic_type of SLAVE_NACK : constant is 1;
    attribute mti_svvh_generic_type of SLAVE_STRETCH : constant is 1;
    attribute mti_svvh_generic_type of TEST_DATA_WRITE : constant is 1;
    attribute mti_svvh_generic_type of TEST_DATA_READ : constant is 1;
end i2c_tb;
